This invention relates to programmable logic devices (PLDs), and, more particularly, to techniques for facilitating the use of function-specific blocks which may be included in such devices.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include “function-specific blocks” (FSBs) in addition to blocks of generic programmable logic resources. Typically, an FSB is a concentration of circuitry on a PLD that has been partly- or fully-hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. An FSB may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented as FSBs include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
While the availability of FSBs on a PLD may lessen the need for programmably implementing such structures in soft logic (e.g., by piecing together and configuring several blocks of generic programmable logic resources), the nature of the functions implemented in FSBs are often those which require inputs and/or outputs that are several bits wide (i.e., multi-bit signals). As a result, significant interconnection resources may be required simply for routing input and output signals to and from FSBs. The need for interconnection resources may be further compounded when FSB output signals undergo additional processing, such as bitwise/logical/mathematical operations, signal conditioning/manipulation, combination with output signals from other FSBs, and the like.
As a consequence, performance and usability bottlenecks may result from the inefficient allocation of interconnection resources for the purpose of routing signals to and from FSBs. Such performance bottlenecks may become acute in those PLD designs wherein the routing needs of the FSBs are accommodated primarily by diverting existing routing resources from the structures that surround the FSBs (e.g., blocks of generic programmable logic resources), such that the inefficient usage of those routing resources may sacrifice the usability of the neighboring structures.
Commonly-assigned U.S. Pat. No. 6,781,408, which is hereby incorporated by reference in its entirety, describes a PLD wherein dedicated input and output routing channels are provided to facilitate the processing, including but not limited to the routing, registering, and/or selection, of input signals supplied to one or more of the FSBs, and of output signals generated by one or more FSBs, while allowing general-purpose interconnection resources to be conserved.
According to that patent, dedicated input and output routing channels may be constructed that include a plurality of selectively-chainable functional units that are programmably configurable to implement, in a relatively localized area, a variety of processing operations (e.g., arithmetic/bitwise/logical/mathematical functions, combinations, signal conditioning operations, etc.) that may be performed on the input signals supplied to one or more FSBs, or on the output signals generated by one or more FSBs.